Prioritized clock selection circuit
US4538272A · kind A · utility
16Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1983 |
| Grant date | Aug 27, 1985 |
| Priority date | — |
| Expiry date | Dec 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A clock selection circuit which selects and enables one of a plurality of clock circuits in response to initialization by a processing unit or detection of failure of an on-line clock circuit. The clock circuits are selected on the basis of a priority arrangement. The clock circuit failure is detected by a retriggerable monostable multivibrator and the selection priority is based on time delays generated by programmed counters associated with each clock circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.