Shift register circuit with multiple, tapped outputs having pull-down transistors
US4538288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1983 |
| Grant date | Aug 27, 1985 |
| Priority date | — |
| Expiry date | Sep 1, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage. Furthermore, a second transmission gate is connected between the output terminal of the source follower transistor and the ground in which after the output signal at the output terminal rises up and falls down once, the second transmission gate is turned on by the signal relating to the output from the stages following the succeeding stage to thereby make the level of the signal when the output signal at the output terminal falls down stable. Thus, undesired potential fluctuation is not generated on the output…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.