Method and apparatus for signaling on-line failure detection
US4539682A · kind A · utility
31Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1983 |
| Grant date | Sep 3, 1985 |
| Priority date | — |
| Expiry date | Apr 11, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/079
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus permitting a multi-module digital system, such as a puter, having built-in test hardware associated with each module, including a plurality of signal processing units to communicate over two wire circuitry not only the existence of a failure of a particular module, but also its causality. This is accomplished by means of a four state signaling circuit interposed between each signal processing unit of a particular module and a module built-in test circuit which operates once an error output is reported by a signal processing unit to provide a further four state indication of the details of the failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.