Clocked buffer circuit using a self-bootstrapping transistor
US4540898A · kind A · utility
9Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1983 |
| Grant date | Sep 10, 1985 |
| Priority date | — |
| Expiry date | Mar 7, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356017
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clocked buffer circuit is provided which uses a self-bootstrapping transistor to provide a full power supply output signal in response to an input signal and a full power supply clock signal. The self-bootstrapping transistor is disabled by a delay circuit prior to the removal of the clock signal so that the output signal is still provided after the removal of the clock signal. That the output signal reaches full power supply is ensured because the disabling effect of the delay circuit is triggered by the output signal itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.