Reduced swing latch circuit utilizing gate current proportional to temperature
US4540900A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1982 |
| Grant date | Sep 10, 1985 |
| Priority date | — |
| Expiry date | Jul 1, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch circuit utilizes a series-gated, emitter coupled logic structure including a current source providing a gate current substantially proportional to temperature for developing an output signal swing substantially proportional to temperature, thereby allowing the output signal swing to have a reduced magnitude at nominal temperatures. The load across which the output signal is developed includes a resistor coupled in series with a semiconductor P-N junction. Emitter areas of emitter-coupled transistor pairs within the latch circuit are mismatched for creating an offset tending to compensate changes in the voltage across the semiconductor junction within the load resulting from the switching action of the latch circuit. A bias circuit maintains the switching threshold reference voltage substantially intermediate the output signal swing. The semiconductor junction within the load of the latch circuit may correspond with the base-emitter junction of a transistor, and an additional load resistor may be coupled to the collector thereof for providing a second output signal swing of increased magnitude isolated from the feedback path of the latch circuit. In an alternate embodiment, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.