Process for the positioning of an interconnection line on an electrical contact hole of an integrated circuit
US4541892A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1984 |
| Grant date | Sep 17, 1985 |
| Priority date | — |
| Expiry date | Aug 10, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improvement to the process for positioning an interconnection line on an electrical contact hole of an integrated circuit, according to which between a photosensitive coating and an insulating coating is interposed an intermediate anti-reflecting coating made e.g. from SiO.sub.2 or amorphous silicon. The SiO.sub.2 intermediate coating, etched after irradiation of the photosensitive material coating, is used as a mask for reactive ionic etching of the insulating coating. Thus, the image of the photosensitive material coating is transferred to the thick insulating material coating. This process is useful especially in the production of integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.