Double bootstrapped clock buffer circuit
US4542307A · kind A · utility
8Cited by
9References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 26, 1983 |
| Grant date | Sep 17, 1985 |
| Priority date | — |
| Expiry date | Sep 26, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01714
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit has first and second boot-strap circuits. The first boot-strap circuit charges the gate of an output MOS transistor to a voltage above a supply voltage when an input signal has a first logic level. The gate of a precharging MOS transistor in the first boot-strap circuit is driven by the second boot-strap circuit so as to precharge a capacitor in the first boot-strap circuit to a voltage above the supply voltage when the input signal has a second logic level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.