Process insensitive CMOS window detector
US4543498A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1982 |
| Grant date | Sep 24, 1985 |
| Priority date | — |
| Expiry date | Sep 16, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/16519
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A CMOS window detector provides outputs which indicate whether an input voltage is within a voltage "window". The window detector includes a bias circuit and first and second inverter circuits. A bias current is established by the bias circuit as a function of a reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FETs are connected to the bias circuit to provide two different mirror currents. The mirror currents are a function of the bias current and the current mirror FET channel shape factors. The input voltage signal is applied to the gates of the current control FETs of the first and second inverters. The window voltage level of each inverter circuit is independent of the other inverter circuit and is determined as a function of the mirror current and channel shape factor of the current control FET. Logic level outputs taken from first and second inverter circuits indicate whether an input signal voltage is within or outside the window created by the window voltage levels of the two inverter circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.