Offset compensated switched capacitor circuits
US4543534A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1984 |
| Grant date | Sep 24, 1985 |
| Priority date | — |
| Expiry date | May 4, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched capacitor type amplifier system including an operational amplifier is provided with compensating capacitive coupling during the non-sampling portion of the cycle from the output of the operational amplifier to its input, to avoid output discontinuities, and to provide compensation for the offset voltage of the operational amplifier. The circuit includes a two phase clock, with the signal input to the input capacitor being alternately sampled and blocked, and the capacitive compensation circuit mentioned above being alternately blocked and connected, respectively, during successive phases of the clock operation. Special circuitry for preventing "clock feed-through" and for implementing a Multiplying Digital to Analog Converter, or MDAC, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.