Apparatus and method for controlling digital data processing system employing multiple processors
US4543626A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1982 |
| Grant date | Sep 24, 1985 |
| Priority date | — |
| Expiry date | Dec 6, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each command is associated with a route comprising a sequence of route vectors, each identifying an operation to be performed to execute the command, as well as the process, or station, to execute the route vector. In response to the receipt of a command, a control block is generated identifying the first route vector in the route associated with the command. Each station has a work queue containing control blocks, which the station retrieves and processes sequentially. The control block is first sent to the work queue of the station to perform the first operation. When the station gets to the control block, it performs the operation required by the route vector, modifies the control block to identify the next route vector in the sequence, and transfers the control block to the work queue of the station to perform the operation required by the next route vector in the route.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.