Process for positioning an interconnection line on an electric contact hole of an integrated circuit
US4544445A · kind A · utility
16Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1984 |
| Grant date | Oct 1, 1985 |
| Priority date | — |
| Expiry date | Mar 16, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process for the positioning of an interconnection line on an electric contact hole in an integrated circuit. According to the invention, one or more conductive layers forming a conductive covering are deposited on the complete integrated circuit. The first conductive layer is deposited by an isotropic process. The interconnection line to be produced is then masked by a resin layer, followed by the successive etching of each conductive layer. Finally, an overetching of these conductive layers is effected in the electric contact hole, followed by the elimination of the resin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.