Synchronizer circuit with dual input
US4544851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1981 |
| Grant date | Oct 1, 1985 |
| Priority date | — |
| Expiry date | Aug 31, 2001 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic "0" and "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic "0" to a logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for a three quarter of a machine cycle to allow any transient conditions within the latch to dampen out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.