Method and apparatus for optimally tuning clock signals for digital computers
US4546269A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1983 |
| Grant date | Oct 8, 1985 |
| Priority date | — |
| Expiry date | Dec 1, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a first searching mode of the control program for the microprocessor, the microprocessor starts with a selected clock input and associated delay circuit and sets the delay circuit to an initial clocking point which is intermediate to the minimum and maximum delay points. The microprocessor then, at each pass of the control program, successively increments the delay period interposed by the delay circuit to cause the clock pulse to arrive later and later in time at the clock input until the associated circuit fails, to indicate the late clocking failure limit. In the second searching mode of the microprocessor control program, the microprocessor starts at the late clocking failure limit and at each subsequent pass of the program successively decrements the delay period interposed by the delay circuit to cause the clock signal to arrive earlier and earlier in time until the semiconductor device fails again, to indicate the early clocking failure limit. The early clocking failure limit and the late clocking failure limit together define the clocking window for the semiconductor device. The microprocessor sets the delay circuit to the mid-point of the clocking window which is the op…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.