Repairable multi-level overlay system for semiconductor device
US4549200A · kind A · utility
83Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1982 |
| Grant date | Oct 22, 1985 |
| Priority date | — |
| Expiry date | Jul 8, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.