Boosting circuit
US4550264A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1983 |
| Grant date | Oct 29, 1985 |
| Priority date | — |
| Expiry date | Mar 30, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A boosting circuit includes a plurality of variable capacitors with controllable capacitance values in accordance with the voltage level at first and second terminals of each of the variable capicitors A plurality of first buffer circuits is located at the first terminal side, each acting to increase the voltage level at the corresponding first terminal to a first level. A single second buffer circuit located at the second terminal side cooperating commonly with the variable capacitors, to increase the voltage level at each second terminal. The first level is thus boosted to a second level which results in an output of the circuit concerned. Each variable capacitor is fabricated by a MOS transistor capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.