Data processing system having hierarchical memories
US4550367A · kind A · utility
14Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1981 |
| Grant date | Oct 29, 1985 |
| Priority date | — |
| Expiry date | Mar 20, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system having hierarchical memories comprised of buffer memories contained in a plurality of central processing units, an intermediate buffer memory and a main memory having a plurality of banks. The intermediate buffer memory and the main memory are controlled under both a swap control method and a set associative control method. These two memories are accessed by address information which includes both bank-selection address bits and set-selection address bits. The bank-selection address bits are partially modified by part of the set-selection address bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.