PM Decoder sample and hold circuit
US4550424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1984 |
| Grant date | Oct 29, 1985 |
| Priority date | — |
| Expiry date | Feb 9, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04H20/49
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An AM stereo receiver decoder is shown. An AM detector produces the stereo L+R signal and a PM detector produces the L-R signal. The PM detector is created from a conventional FM detector that employs an input limiter driving a balanced multiplier. The limiter also drives a tuned circuit which provides quadrature drive to the multiplier. An integrator connected to the FM detector converts the response to a PM decoder. A large value inductor is simulated to appear across the integrator so as to create a low modulation frequency resonance at a subaudible frequency thereby providing a controlled pilot tone response. The inductor is simulated by the action of a first G.sub.m amplifier driving a capacitor which drives a second G.sub.m amplifier having an output coupled back to the input of the first G.sub.m amplifier. The capacitor is switched by means of a series connected switch that disconnects the capacitor when the AM exceeds a predetermined value. This means that when the L+R negative modulation peaks exceed some predetermined value the simulated inductor acts to short out the L-R signal channel. Since the switch is in series with the capacitor, the charge cannot vary when the swi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.