High switching speed semiconductor device containing graded killer impurity
US4551744A · kind A · utility
6Cited by
5References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 1982 |
| Grant date | Nov 5, 1985 |
| Priority date | — |
| Expiry date | Jul 30, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/241
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device for controlling a current comprises a pn junction formed of a high resistivity region and a relatively low resistivity region, a graded distribution of dislocation density is formed in the high resistivity region and decreases with an increase in distance from the pn junction, also graded distribution of lifetime killer concentration is formed in the high resistivity region and decreases with an increase in distance from the pn junction in correspondence with the graded distribution of dislocation density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.