Multi-chip carrier array
US4551788A · kind A · utility
Inventors
Key dates
| Filing date | Oct 4, 1984 |
| Grant date | Nov 5, 1985 |
| Priority date | — |
| Expiry date | Oct 4, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09854
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip carrier array in which the individual carriers are defined by two perpendicular sets of parallel scribe lines which bisect the major axes of a plurality of equally-spaced oblong perforations. At the point of intersection of any two perpendicular scribe lines, the major axes of two such perforations intersect and bisect the right angles formed by said two perpendicular scribe lines. All other oblong perforations have their major axes perpendicular to the scribe lines. On the bottom surface of the array, metallic solder pads are located at opposite ends of each oblong perforation, and conductive material from each pad extends to the top surface of the array. Trace conductors on the top surface can be connected to these pad extensions. The trace conductors, in turn, will be connected to various connection points on an IC chip mounted in the center of the top surface of an individual carrier. Because the axis of any oblong perforation forms at least a half-right angle with its intersecting scribe line, the solder pads located at opposite ends of each oblong perforation can be separated by a gap sufficiently wide to permit electrical testing of the chips prior to the divisi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.