Multilayer ceramic substrates with several metallization planes
US4551789A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1982 |
| Grant date | Nov 5, 1985 |
| Priority date | — |
| Expiry date | Dec 13, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0306
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention concerns a ceramic substrate for mounting semiconductor integrated circuits. The substrates include at least a first and second patterned metallization layer which respectively form conducting planes that are parallel to each other but separated by a thickness of insulation. The pattern metallization of at least the first plane includes signal conductors for joining the contacts of the integrated circuit chip to pins provided in the substrate for connecting the substrate and chip to a circuit board. In accordance with the invention, the metallization of the second plane includes shorted conductor loops that follow the contour of the signal conductors. The shorted loops of the second plane metallization includes branches which extend parallel to both lateral sides of a respective signal conductor. In accordance with the invention, the branches of the loops are joined at their ends.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.