Fabrication of metal lines for semiconductor devices
US4551905A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1983 |
| Grant date | Nov 12, 1985 |
| Priority date | — |
| Expiry date | Nov 9, 2003 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.