Fabrication method for controlled via hole process
US4552831A · kind A · utility
7Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 6, 1984 |
| Grant date | Nov 12, 1985 |
| Priority date | — |
| Expiry date | Feb 6, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/0017
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for forming via holes having a rounded sidewall profile includes exposing a layer or organic positive photoresist to a formic gas plasma while the surface of the photoresist layer is bombarded with ions and electrons in a high voltage biased environment in which the photoresist layer is capacitively coupled. The photoresist layer may be exposed to UV light either before or after the formic gas plasma step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.