Planarizing layer for semiconductor substrates such as solid state imagers
US4553153A · kind A · utility
20Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1983 |
| Grant date | Nov 12, 1985 |
| Priority date | — |
| Expiry date | Oct 21, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F77/331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device is disclosed comprising a non-planar semiconductor substrate and a planarizing layer thereon, the planarizing layer having a maximum thickness that is no greater than about 3.mu. and a planarization factor P.gtoreq.1.0. In a preferred embodiment, the layer comprises a polymer formed from a liquid monomer coated onto the substrate and thereafter polymerized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.