Circuit and process for chrominance decoding with analog or digital delay line in a television system of a pal or secam type
US4553156A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1983 |
| Grant date | Nov 12, 1985 |
| Priority date | — |
| Expiry date | Dec 8, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/64
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a matching circuit for connecting a chrominance decoding integrated circuit normally connected by terminals to a conventional analog delay line so as to make it compatible with a digital delay line. This matching circuit comprises a switch connecting alternately each of the outputs of the integrated circuit to an analog-digital convertor connected to a digital delay line, to a digital-analog convertor, then to a switch routing the signal alternately to each of the two summators whose other inputs receive directly the output of the integrated circuit. The summators supply then respectively the chrominance signals R-Y and B-Y.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.