Latching comparator with hysteresis
US4554468A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1983 |
| Grant date | Nov 19, 1985 |
| Priority date | — |
| Expiry date | Jul 1, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/2897
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self latching comparator circuit has upper and lower input offset voltages associated therewith to establish hysteresis in response to a differential input signal. The comparator circuit comprises a differential amplifier adapted to receive a differential input signal and first and second parallel current mirror circuits for producing upper and lower input offset voltages when each are respectively activated. Antisaturation means are provided for preventing the current mirror circuits from saturating. An output circuit is also provided which does not load the differential output and therefore provides for a well controlled hysteresis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.