Offset voltage correction network for instantaneous floating point amplifier
US4554511A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1982 |
| Grant date | Nov 19, 1985 |
| Priority date | — |
| Expiry date | Sep 29, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/304
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an instantaneous floating point amplifier which continuously generates an offset correction voltage level for each possible gain word controlling an internal cascaded amplifier. The offset voltage levels are digitized and stored until an input data signal is received. A portion of the output analog-to-digital converter system for the floating point amplifier is utilized on a time sharing basis to regenerate an analog offset correction voltage. The offset correction voltage is input into a summing network inserted into the amplifier circuit between internal preamplifier and amplifier components. When the input signal has been grounded, the offset correction voltage is disconnected from the input summing network and the floating point amplifier is cycled through its gain operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.