CMOS Operational amplifier
US4554515A · kind A · utility
218Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1984 |
| Grant date | Nov 19, 1985 |
| Priority date | — |
| Expiry date | Jul 6, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45674
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Two input stages (10,12) are interconnected so that their input common mode voltage ranges to one side of signal ground are combined to provide a common mode voltage range substantially equal to the supply voltage. One stage has N-channel differential input transistors (N1,N2), while the other stage has P-channel differential input transistors (P3,P4). The input current branches of the stages are interconnected by current mirror transistors (N6,N7) so that signal current is shared. The output (22) is taken from one branch of the N-type stage (10) and coupled to an output stage (24) with frequency compensation (C,R).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.