Static RAM cell
US4554644A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1982 |
| Grant date | Nov 19, 1985 |
| Priority date | — |
| Expiry date | Jun 21, 2002 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static RAM cell (11) is constructed utilizing low resistivity positive and negative power supply leads (13,14), thus eliminating the problem of instability of the data stored within the cell. The negative power supply lead is formed of a first layer of low resistivity polycrystalline silicon/tantalum silicide, and the positive power supply lead is formed of a second layer of polycrystalline silicon. The use of a low resistivity negative power supply lead causes the voltage drop on the negative power supply lead to be substantially reduced as compared with prior art devices, thereby providing during the read operation substantially equal voltages to the gates of the two bistable transistors of each cell, thus eliminating the problem of instability during reading. Depletion load devices (11,12) are formed utilizing the layer of polycrystalline silicon as the source, drain and channel and the layer of polycrystalline silicon/tantalum silicide as the gate. In this manner, silicon area is not required to form the depletion load devices, thus minimizing cell size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.