Semiconductor memory device
US4554646A · kind A · utility
18Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1983 |
| Grant date | Nov 19, 1985 |
| Priority date | — |
| Expiry date | Oct 17, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.