Patent · US Expired

Output interface for a three-state logic circuit in an integrated circuit using MOS transistors

US4555644A · kind A · utility

7Cited by

5References

3Claims

0Family size

Assignee

SGS-Ates Componenti Elettronici S.p.A. · IT

Inventors

Daniele Devecchi · Desio, IT
Guido Torelli · Pavia, IT

Key dates

Filing date	Dec 12, 1983
Grant date	Nov 26, 1985
Priority date	—
Expiry date	Dec 12, 2003

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/09429
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An output interface which includes a capacitor which is charged to a relatively high voltage by a voltage source which may have a high internal impedance, and a switching circuit which is controlled by an output of the associated logic circuit and which connects the capacitor with a gate electrode of a transistor of the final stage of the interface in order to bias it at a higher voltage than that of the power supply only during a prespecified logic state of the logic circuit and which keeps the capacitor essentially isolated (i.e.--floating) during any other logic state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.