Refresh circuit for dynamic memory of a data processor employing a direct memory access controller
US4556952A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1981 |
| Grant date | Dec 3, 1985 |
| Priority date | — |
| Expiry date | Aug 12, 2001 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.