Programmable redundancy circuit
US4556975A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1983 |
| Grant date | Dec 3, 1985 |
| Priority date | — |
| Expiry date | Feb 7, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.