Logic families interface circuit and having a CMOS latch for controlling hysteresis
US4558237A · kind A · utility
9Cited by
10References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1984 |
| Grant date | Dec 10, 1985 |
| Priority date | — |
| Expiry date | Mar 30, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface circuit to couple logic signals from a logic gate of one kind of logic family to a logic gate of another operating at different logic state voltages, where a latch circuit is used with the first of two cascaded inverters to provide the desired interface circuit signal characteristics. One inverter is provided with a supply reduction threshold means as is another inverter in the latch so that the two inverters perform substantially similarly to one another. The latch allows independent adjustments of opposite direction logic level transitions to provide a desired noise margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.