Incremental encoder synchronous decode circuit
US4558304A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 24, 1983 |
| Grant date | Dec 10, 1985 |
| Priority date | — |
| Expiry date | Feb 24, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronous decode circuit for an incremental encoder is disclosed which comprises analog-to-digital converters for converting in phase and quadrature encoder signals to transistor-to-transistor logic (TTL) compatible signals, a latch for receiving current logic level signals and the previous logic level signals for a gray code, a programmable read only memory (PROM) for decoding the logic level signals and generating clock and direction enable signals, and gating logic connected to the PROM for gating clock and direction signals to counters of the system, the counters are connected to a latch under control of the computer to latch the count of movement in preselected directions for the computer. In another embodiment the PROM includes scaling jumper means or error detection means or both for, respectively, adjusting the range of measurement (scale factor) and indicating error in the logic level signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.