Semiconductor memory device
US4558434A · kind A · utility
6Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1984 |
| Grant date | Dec 10, 1985 |
| Priority date | — |
| Expiry date | Jan 25, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.