Interleavers for digital communications
US4559625A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1983 |
| Grant date | Dec 17, 1985 |
| Priority date | — |
| Expiry date | Jul 28, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved method and apparatus for interleaving block codes exploits helical symmetry whereby correspondingly positioned code symbols of code words of length n interleaved to depth i, i<n, are separated on the channel by .alpha.i+.beta. symbol intervals where 1+.gamma..gtoreq.i is averaged over the i correspondingly positioned symbols and .alpha.and .vertline..beta..vertline. are integers >1. The requirement for synchrony is reduced to a period counted modulo n instead of mod (n.times.i). For the case i=n-1, the total interleaving delay is reduced to 2(n-1)n and phase dependence of burst error onset is minimized. The performance of the de-interleaver is enhanced through a pseudo fade detector implemented by creating erasures prior to decoding, at certain positions for codewords subsequent to confirmed error. Synchronization of interleaver and de-interleaver is accomplished in apparatus which inspects all c contiguous bit patterns corresponding to a c bit synch symbol. To each c contiguous bit pattern of the data stream there is associated a probability counter for incrementing when the synch pattern is detected and decremented otherwise. Maximum probability establishes synch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.