"Clocked self booting logical ""EXCLUSIVE OR"" circuit"
US4562365A · kind A · utility
9Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1983 |
| Grant date | Dec 31, 1985 |
| Priority date | — |
| Expiry date | Jan 6, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A solid state logical "EXCLUSIVE OR" circuit for implementation in NMOS circuitry utilizes existing non-overlapping clock pulses for self-booting circuit conditioning, enabling ultrafast propagation times and minimal power drain during circuit operation, whereof row driver circuit design concepts are utilized and silicon area is minimized and two, non-overlapping, low impedance pulses, normally present in the circuit environment are utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.