Directory test error mode control apparatus
US4562536A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1983 |
| Grant date | Dec 31, 1985 |
| Priority date | — |
| Expiry date | Jun 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.