Floating point digital differential analyzer
US4563749A · kind A · utility
1Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1982 |
| Grant date | Jan 7, 1986 |
| Priority date | — |
| Expiry date | Dec 14, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a floating point digital differential analyzer, multiplication and division of constants are carried out by an adder which truncates a summation SDY.sub.i of l secondary increments calculated by ##EQU1## into a third increment having an n-bit mantissa including a sign bit, and an integrator for carrying out an integration of EQU R.sub.i :=R.sub.i-1 +Y.sub.i .multidot..DELTA.X.sub.i -.DELTA.Z.sub.i irrespective of a value of a first increment .DELTA.X.sub.i to generate .DELTA.Z.sub.i from R.sub.i.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.