Postage meter with power-failure resistant memory
US4564922A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1983 |
| Grant date | Jan 14, 1986 |
| Priority date | — |
| Expiry date | Oct 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00411
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A security system for a postage meter includes two memories, one of which is an electronically programmable READ-ONLY memory having non-volatile storage, while the second memory is a shadow RAM which is a composite memory having a first section composed of a volatile RAM and a second section composed of non-volatile storage. During a power outage, a computer strobes the second memory to transfer data from the volatile section to the non-volatile section. Upon restoration of the power, a transfer circuit which includes a detector of the incoming power directs the transfer of at least a portion of the stored data in each of the memories to the computer for a comparison to determine if any data has been altered by the loss of power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.