Remote data link address sequencer and a memory arrangement for accessing and storing digital data
US4564937A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1983 |
| Grant date | Jan 14, 1986 |
| Priority date | — |
| Expiry date | Dec 22, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.