Noise reduction circuit of synthetic speech generating apparatus
US4564954A · kind A · utility
6Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1983 |
| Grant date | Jan 14, 1986 |
| Priority date | — |
| Expiry date | Jan 5, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L13/08
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A speech synthesizer may generate random sounds during die-down after power turn-off. To prevent such sound generation, the synthesizer clock circuit is grounded by an FET simultaneously with power turn-off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.