Method of forming localized epitaxy and devices formed therein
US4566914A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 1983 |
| Grant date | Jan 28, 1986 |
| Priority date | — |
| Expiry date | May 13, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure for isolating circuit structures in closely packed integrated circuits, and a method for making the same. The isolation structure includes a semiconductor body having a surface, an insulatory layer on the surface having an aperture and an offset adjacent to the aperture, the aperture and offset being filled with epitaxial semiconductor material, at least a portion of the epitaxial material being single crystal semiconductor, said structure being used for the fabrication of standard semiconductor devices. The method uses conventional processing techniques that require a minimum of additional cost over prior art, and yet provide a high degree of device isolation and density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.