Clamp circuit
US4567388A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1983 |
| Grant date | Jan 28, 1986 |
| Priority date | — |
| Expiry date | Oct 3, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00307
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This relates to a circuit for clamping the voltage across first and second terminals (in this case the gate and source electrodes of a power MOSFET) in response to the receipt of a signal indicating a load fault. An input turnaround transistor receives the signal indicative of the fault and generates a current in response thereto which is applied to the base of a switching transistor. When this current exceeds a predetermined value, the switching transistor turns on which in turn causes a buffer circuit including a PNP transistor to turn on. When the buffer circuit turns on, current is drawn through a zener diode which is coupled to the second terminal. Thus, the clamping circuit between the gate and source terminals equals the voltage drop across the zener diode plus that dropped across the buffer circuit plus the saturation voltage of the switching transistor. Resistors are provided in the buffer circuit to provide for a certain amount of adjustment of the clamping voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.