MIS Device employing elemental pnictide or polyphosphide insulating layers
US4567503A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1983 |
| Grant date | Jan 28, 1986 |
| Priority date | — |
| Expiry date | Jun 29, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Metal-insulator-semiconductor devices are formed on III-V semiconductors utilizing a pnictide rich insulating layer. The layer may be applied by vacuum evaporation, sputtering, chemical vapor deposition, and from a liquid melt. Gallium arsenide, indium phosphide, and gallium phosphide substrates are insulated with an alkali metal high pnictide polypnictide, preferably a polyphosphide, having the formula MP.sub.x where x is equal to or greater than 15, including new forms of phosphorus grown in the presence of an alkali metal where x is much greater than 15. A KP.sub.15 layer is preferred. They may also be insulated with a layer of a solid elemental pnictide, namely phosphorus, arsenic, antimony or bismuth applied by one of the above named processes. An elemental phosphorus layer is preferred. A silicon nitride, Si.sub.3 N.sub.4, layer may be added on top of the pnictide layer to increase the breakdown voltage of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.