Method of fabricating semiconductor devices having a diffused region of reduced length
US4567641A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 1984 |
| Grant date | Feb 4, 1986 |
| Priority date | — |
| Expiry date | Sep 12, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N.sup.+ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N.sup.+ SOURCE through the same window. The etchant removes most of the N.sup.+ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N.sup.+ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.