Flexible timing circuit
US4568841A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1983 |
| Grant date | Feb 4, 1986 |
| Priority date | — |
| Expiry date | Mar 28, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention includes a counter device which counts pulses from a pulse source and provides the basis for a control gate signal. Logic circuitry is connected to the counter device and through said logic circuitry there are provided the leading edge, the interim voltage level signal, and the trailing edge of said control gate signal. The counter device is connected from at least two latter stages to said logic circuitry to provide two possible trailing edges, which in turn selectively define two different length gate signals. Said logic circuitry is further connected to address signal circuitry and in response to a first address provides a control gate signal of a first length and in response to a second address provides a control gate signal of a second length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.