Circuit arrangement for serial digital filters
US4569031A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 1983 |
| Grant date | Feb 4, 1986 |
| Priority date | — |
| Expiry date | Mar 21, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Such digital filters process digital input data occurring during short pulses of a filter sampling signal (fa) in the pure binary code and in two's complement notation. They contain a parallel-to-serial converter (pw) at the input end, at least one adder (ad), at least one shift register used as a status register (z), at least one multiplier circuit (m1) to which an input-data-dependent signal and a factor which is constant at least during the multiplication are applied as a multiplier and a multiplicand, respectively, and a serial-to-parallel converter (sw) at the output end. The status register (z) has, in addition to a number of stages determined by the number of digits of the input data, a number of stages equal to the number of digits of the multiplicand. The parallel-to-serial converter (pw) is followed by a digit complementer (se) which increases the number of digits of the output signal of the parallel-to-serial converter (pw) to that of the status register (z). The function of the multiplier circuit is implemented with a sign-signal repeater (vw) and a tap on at least one stage (r) of the status register (z) which tap is connected to the input of the sign-signal repeater (…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.