Self booting logical AND circuit
US4570085A · kind A · utility
10Cited by
6References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 17, 1983 |
| Grant date | Feb 11, 1986 |
| Priority date | — |
| Expiry date | Jan 17, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A solid state logical "AND" circuit implementation in NMOS circuitry has clock pulse conditioning providing self booting voltage levels for ultra fast propagation times and minimal power dissipation, where memory row driver concepts are utilized and silicon area is minimized, and two, low impedance, non-overlapping clock pulses, normally present in the environment are utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.