High-speed sense amplifier circuit with inhibit capability
US4570090A · kind A · utility
1Cited by
10References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1983 |
| Grant date | Feb 11, 1986 |
| Priority date | — |
| Expiry date | Jun 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit for use with a directory memory chip in which the output of a corresponding memory cell is sensed and output signals representing the sensed bit state are provided to first and second output ports. The signal provided to the first output port can be selectively inhibited, although, when not inhibited, the signals applied to the first and second output ports occur simultaneously. The inhibiting function may be performed by a dual-emitter circuit and switchable current source in one of two sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.